#FPGA dorks. I'm running into an issue where #vivado says: multiple drivers on MMCM pins when I use a known good block (LVDS deserializer from appnote xapp523) in the vivado block diagram for a 7 series #xilinx #zynq part (snickerdoodle black). I get the error even if I pin out directly to top level pins. I hate using the gui because it hides too much magic. Has anyone hit this madness before?
I'm trying to deserialize a 1.024 Mbps 8b10b lvds to get it on the linux side for storage on disk.
FPGAspreading way of synthesis.
- Download `tar`archive : 125GB
- Unflat archive : +125GB
- Launch installer and install : + 210GB
Total space required for full installation : 460GB !
Hmm qu'est-ce que je supprime pour faire de la place ?
On the positive side, the files reported unreadable were all various things under /work/xilinx/Vivado/2019.2/...
So, if I'm lucky I haven't lost anything important and Vivado has finally proved itself useful... as a 25GB ablative shield for the rest of my project data on that volume...
It is currently not possible to import a Block Design into a Non-Project flow in Vivado. Block Designs are the foundational construct of IP Integrator-based designs.
The Block Design configuration can be exported as a TCL script which can then be sourced in a build script for Project Scripted flow, making the repository storage overhead very low.
@WillFlux This is sometimes helpful. In the #Xilinx tools I tend to bump the version number and rebuild if it misses timing by a small amount. Promising #reproducibility in these tools is hard. In #Vivado it's only "guaranteed" if you turn off all of the parallel processing. And even then I think you really need to run it on the same hardware. And even then I wouldn't be confident, because I don't think anyone at Xilinx tests for reproducibility. A 'fix' might pre-process to remove all comments.
and demo that on the pico ice
