Understand CPU Branch Instructions Better
https://chrisfeilbach.com/2025/07/05/understand-cpu-branch-instructions-better/
[High-level language computers] are aesthetically appealing to those not familiar with modern compiler writing technology. It is acknowledged that code generation may be simpler for a high-level language computer. What needs to be made more fully understood is that a high-level language instruction set does not eliminate the need for compilers, nor does it greatly simplify them. The need and complexity of compilers extends far beyond code generation. The amount of code necessary for preprocessing, lexical analysis, syntax analysis, assembly, optimization, loading, error detection, error recovery and diagnostics often dwarfs the part of the compiler concerned with code generation. The level of the target computer does not seem to have enough of an effect on the size of a compiler to warrant a totally new architecture.ref: https://dl.acm.org/doi/pdf/10.1145/800053.801914
¿Algún experto en sistemas operativos o en arquitectura de computadores me puede comprobar que este diagrama es correcto? Lo acabo de crear en @drawio partiendo de varios gráficos de "Sistemas Operativos" de Gary Nutt (Ed. Pearson).
¡Mil gracias!
Hey everyone involved in #ComputerScience, are you looking for a #job in #academia?
Aalto University in Finland has several positions open for assistant professors. The topics include #MachineLearning, #Programming, #ComputerArchitecture, #CyberSecurity, #SoftwareEngineering and Human-Computer Interactions.
https://www.aalto.fi/en/department-of-computer-science/assistant-professor-positions
If it's not an API, it's an implementation detail.
A nicely-phrased distinction: “On the technical side, I want to stress that there’s no such thing as an undocumented API (or private API). By definition an API is something that’s meant to be called by apps. Things that aren’t APIs are implementation details. And when you use that term it’s easier to evaluate your choices.” — Quinn “The Eskimo!”
Which is all too reminiscent of a common outcome among apps:
"With a sufficient number of users of an API,
it does not matter what you promise in the contract:
all observable behaviors of your system
will be depended on by somebody.” — Hyrum's Law
Platform providers would usually prefer to follow the model “Everything which is not allowed is forbidden" while developers are fond of "Everything which is not forbidden is allowed”.* The former avoids breaking quite as many apps and can deeply annoy, err, limit app developers, while following the latter makes non-breaking platform changes difficult to impossible, and increases support and testing.
At the intersection of those two models is app instability, angst, and architectural limits.
And yes, there are inevitably cases where API designs are just broken, or where the designs reach their architectural limits, and those then either stymy further work, or might get incompatibly un-broken, or preferably get replaced in parallel with better and more capable designs and the older APIs deprecated and removed.
How you design replacements for your API limits is part of your design too, but a part frequently ignored. As are app upgrades.
Limited API designs I've met have included an eight-byte password hash buffer, and APIs featuring 32-bit addressing for storage and memory.
*I'll leave any discussions of Misters Dillon and Cooley for another time.
@jfmezei :How long are data blocks for each entry in the in-CPU cache? 64 bits ? 128 bytes ? 1 page ?
It varies. Most implementations will use one cache block size at a time at a given cache level, but that size and the size and the organization of the caches varies.
:Does this vary from architecture to architecture or even inside an architecture?
Yes. Alpha caching varied by processor and by implementation, all within the limits of the Alpha architecture.
:Is it totally transparent when writing at OS level?
Totally transparent? No.
Details, such as what was locally called word tearing, alignment, memory timing, and memory lock processing, all get involved.
Similar requirements can arise in apps.
There are a few other wrinkles I’d prefer to not meet again, too.
Mostly transparent? Yes.
:And in multi core with coherent caches, when a core does a write to RAM, does memory controller propagate this to all other cores in case they have it cached? or does memory controller know which core has what in cache and send only relevant updates?
It depends. Most of what I’ve met will mark the cache contents as being invalid, and will await the next opportunity to wait for main memory to load the data, or to wait for a load from L3, or such. I can’t recall ever working on a cache-coherent multiprocessor that tried to reload the cache everywhere.
Alpha could load cache speculatively, or explicitly, or evict as needed.
http://bitsavers.org/pdf/dec/alpha/system_reference/Alpha_System_Reference_Manual_Version_7_1997.pdf
WP has a reasonable description, as well:
https://en.wikipedia.org/wiki/Cache_(computing)
Deeper still:
https://www.cs.swarthmore.edu/~kwebb/cs31/f18/memhierarchy/caching.html
More for amusement, figures 5 and 6 nicely show the shifting scale of the complexity of modern computer systems:
https://www.computer.org/csdl/journal/ts/2021/06/08704965/19HKUhJMVAQ
#digitalequipment #dec
#alpha #computerarchitecture #retrocomputing
Energy-efficient memory innovation: SOT-MRAM #MemoryTechnology could replace cache memory in #ComputerArchitecture in the future // #SustainableComputing #SOTMRAM #SpinOrbitTorque #OrbitalHallEffect @NatureComms @ERC_Research @HorizonEU #MainzUniversity
https://nachrichten.idw-online.de/2025/02/06/toward-sustainable-computing-energy-efficient-memory-innovation
Inside SiFive’s P550 Microarchitecture
https://old.chipsandcheese.com/2025/01/26/inside-sifives-p550-microarchitecture/
"The P550 is a 3-wide out-of-order core with a 13 stage pipeline. Out-of-order execution lets the core move past a stalled instruction to extract instruction level parallelism. It’s critical for achieving high performance because cache and memory latency can be significant limiters for modern CPUs."
RISC-V Vector Extension overview http://0x80.pl/notesen/2024-11-09-riscv-vector-extension.html
"The goal of this text is to provide an overview of RISC-V Vector extension (RVV), and compare — when applicable — with widespread SIMD vector instruction sets: SSE, AVX, AVX-512, ARM Neon and SVE.
[…]
The vector extension is quite a huge addition. It adds 302 instructions plus four highly configurable load & store operations."
Bob Supnik breaks the CVAX to make COBOL run faster:
#introduction #house #housemd #programming #computerarchitecture #computerscience #compsci #breakingbad #ultrakill #speedrun #transbian #transfem #EldenRing
so here goes nothing.
I'm a 20 yr old trans woman who's learning comp sci at Reykjavík University, I'm highly interested in computer science and more generally computer architecture (at least currently).
My main interests besides computer science are music and then i flip between BB universe and House M.D
Whenever I find a new obsession I get very very hyper-focused on it and will spend the next month basically only focusing on it. I tend to play ULTRAKILL about bi-monthly, I speedrun the game a bit, it's one of my main interests. I also play a lot of (too much) elden ring, I've beaten it around 5-6 times at this point(still havent beaten the final boss of the dlc tho...)
Follow if you have any of these interests
RISC-V State of the Union — current highlights and roadmap of RISC-V by RISC-V's chief architect
https://yewtu.be/watch?v=_oLVPFQvJbI
Slides: https://riscv-europe.org/summit/2024/media/proceedings/plenary/Tue-11-30-Krste-Asanovic.pdf
Great #ConnectionMachine + #Feynman story!
“By the end of that summer of 1983, Richard had completed his analysis of the behavior of the router, and much to our surprise and amusement, he presented his answer in the form of a set of partial differential equations. To a physicist this may seem natural, but to a computer designer, treating a set of boolean circuits as a continuous, differentiable system is a bit strange.”
#computerhistory #computerarchitecture https://mastodon.scot/@simon_brooke/112354279945181945
@spiralganglion 
CM-1 history
Thank you for posting your thread!
I particularly enjoyed Tamiko Thiel’s 1992 + revised ‘The Design of the Connection Machine’ article.
@jfmezei Assembler floating point? Some.
OpenVMS didn’t have any FP in the kernel when last I checked, and the operating system drivers didn’t have FP.
Whole lot of integer, though.
There was more than a little FP code in the distribution kit in user mode, though.
And in the compilers, obviously.
I don’t know off-hand what the graphics drivers were doing with FP, if anything.
There was a fifty-some page design and detail spec created for the Alpha-to-Itanium port, around floating point. Most of the hassles there involved the migration of existing code and data to IEEE floating point, or of using newly-created routines that emulated VAX FP on Itanium. Alpha had both IEEE and VAX FP, so various existing code was not switched. Itanium used IEEE and lacked VAX FP.
Amusingly, it was possible for a faulty floating point accelerator to cause the VAX/VMS kernel to bugcheck in the lock manager though, as occasionally happened with FP780 on VAX-11/780. This bugcheck even though the lock manager had no floating point, it did have integer multiply, and FP780 also accelerated integer multiply. Hence, boom.
Ignoring shaders whether Apple Metal or otherwise, and ignoring OpenCL and other such code, and ignoring other GPU-accelerated processing, and ignoring co-processor boards, all which can do their own thing with their own processing, I/O controllers only deal with the *host* instruction set when the host is executing something from the controller firmware store (think “ROM”), whether that’s native instructions or something else like EFI (UEFI) byte code.
https://developer.apple.com/metal/shader-converter/
https://en.wikipedia.org/wiki/OpenCL
https://uefi.org/specs/UEFI/2.10/22_EFI_Byte_Code_Virtual_Machine.html
See also CUDA, Vulkan, DirectX, etc.
TL;DR: the design of modern computers has shifted substantially from the simplistic scattering-of-boxes conceptual descriptions that were (and still are?) taught in many computing classes. Most (all?) modern computers have numerous different processors and instruction sets, with different data types, with multiple operating systems, etc., all active in parallel.
@jfmezei Usually, yes. But like most things in IT, details can vary.
VAX has a wad of CVT conversion instructions, among other wads of instructions including the vector extensions, for instance. VAX offers instructions for pretty much everything to everything (everything circa 1978) and either has an instruction, or maybe has a macro.
For VAX floating point details, see section 9.9 here:
https://docs.vmssoftware.com/docs/VAX_MACRO_INSTRUCTION_SET_REF.pdf#page236
Details here will vary by architecture, and often by implementation within architecture. (q.v. Alpha extensions including the byte-word extension, and Arm SBSA, etc.)
Here’s an Alpha intro, as Alpha was effectively VAX with most of the latent VAX limits removed (not the least of which were the condition codes):
https://www.cs.cmu.edu/afs/cs/academic/class/15213-f98/doc/alpha-guide.pdf
Alpha too has a wad of CVT conversion instructions.
The wrinkle with C code can be the implicit conversions that can (necessarily) arise when mixing data types. I’m not entirely certain a compound if {} else {} and a ?: ternary will produce the same outcome for all possible variations, and I’ve been using C for... for a while.
<voice=buzzlightyear>And UB, UB everywhere.
C looks kinda like a weird PDP-11 in various ways.
If you want to view the instructions of recent architectures, visit godbolt.
Account migrated! It's new #Introduction time!
B.S. ECE from UT Austin, M.S. ECE, minor in #CompSci from Georgia Tech. Focus on Embedded Systems and #ComputerArchitecture for both.
My day job is embedded systems with a specialization in #cryptography.
My not-job is #VR #indiedev, creating things people are too cowardly to do were it not for me. I make videos about those experiments, and also comedically misapplying #mathematics to #fandom, #lgbt, and #poly spaces.
