Recent searches

No recent searches

Search options

Only available when logged in.
sigmoid.social is one of the many independent Mastodon servers you can use to participate in the fediverse.
A social space for people researching, working with, or just interested in AI!

Administered by:

Server stats:

588
active users

sigmoid.social: AboutProfiles directoryPrivacy policy

Mastodon: AboutGet the appKeyboard shortcutsView source codev4.4.3

#pl

1 post1 participant0 posts today
Continued thread
Ross Duncan

Job ad 🧵 2/2
Quantinuum are looking for software engineer to help design and implement quantum programming languages. You need to have OPINIONS about types. Full-time, permanent, based in Cambridge in England.
#jobad #quantum #quantumcomputing #pl #proglang #guppylang #types

jobs.eu.lever.co/quantinuum/6a

jobs.eu.lever.coQuantinuum - Research Software Engineer - Quantum SoftwareQuantinuum are seeking a Research Software Engineer to join our growing Quantum Software team in Cambridge, UK. In this role, you will help shape the design and implementation of the Guppy quantum programming language and contribute to the next generation of the TKET quantum compiler. This is a unique opportunity to work at the intersection of software development, compiler design, and quantum computing research. You will collaborate closely with a small, dynamic team throughout the full development lifecycle — from research and design to programming and testing — with the freedom to think independently and make a real impact.
*
NoCanDo

Some frustrating things I have learnt during my PhD about low level ASIC design, that I haven’t entirely seen reflected in #PL research on hardware.

1. For all the PL research on hardware, SPICE is indispensable for circuit simulations. Pretty much everything else is behind paywalls or unusable. Analog and mixed signal simulations are super important.

2. Synchronous hardware, which is the standard route for hardware design has been done to death. It’s not necessarily the most challenging form of hardware design and verification. It’s still interesting.

3. Hardware at an an analog or mixed signal level really doesn’t compose the way one might naively expect. It really doesn’t. For example, buffer delays won’t compose linearly when you chain them together. When reasoning about delays it is important to consider how much any given module is “loaded” and “driven”.

4. Transistor sizing is a valuable tool for realising various delays and changing the drive of a device. A large delay cell can be obtained by cleverly resizing transistors on a single buffer instead of chaining buffers together.

5. You can’t just put test probes willy-nilly to test for weird effects. Your probes might end up adding load and increasing delays.

6. You really shouldn’t insert extra flip flops when compiling down to RTL level. Ever. No excuses. Latches are even worse. At the same if the designer wants to put a latch in there, you should let them do it.

7. It is important for a designer to be able to see the compiled output (at least the RTL) and match it to their design. This is because all manner of weird effects show up when one goes to lower level representations of a circuit. Thus the designer has to go back and forth between various levels of the design. This means that unlike software, aggressive optimisation in hardware might actually be a bad thing. Conversely designers remain wary of high level combinators precisely because they don’t trust the compilers to do what they want them to do. One engineer told me that hardware engineers even dislike generate blocks in vhdl and Verilog. Fine grained control and understanding is more important than some super high level combinators.

8. The exact same piece of hardware can be repurposed to different uses depending on where you plug it in. A Q flop in a self timing circuit can become a metastability containing latch in a circuit manipulating clocks. Any semantics assigned to hardware must take this into account.

chris actual

Relegation scrap matches can be unpredictable, but a match between two relegated teams sounded like it could be a snooze-fest. I took a chance on #LEISOU and omg I am glad I did lol.

Ref injured and taken out of match? ✅
Jamie Vardy blowing the whistle of the downed ref to stop play? ✅
(A very conservative) 12 mins of stoppage time? ✅

#premierleague#pl#soccer
George Z

Fediverse #PL #academia people, if this paper isn't out there please realize it for me:

A paper that shows the popularity (usage in classrooms, projects, papers) of a programming language for every geographic region.

*
Jan de Muijnck-Hughes

A *gentle* reminder that, I have a funded #PhD position for UK students, available with myself and @bentnib

This project will be looking at developing new methods for asserting the resilience of existing communicating systems by developing new static analysis methods derived from advanced programming language research.

Deadline for getting in contact is: Thursday 20th March 2025

You will belong to @StrathCyber and @mspstrath, as well as gaining access to @spli

strath.ac.uk/studywithus/postg

www.strath.ac.ukTowards Type-Driven Assurance of Communicating Systems | University of Strathclyde
#PL#Idris#TypeTheory
TrendingLive feeds
About